1. Field of the Invention
The present invention relates to a semiconductor device which improves a connection between a bit line and a cell of dynamic access memory.
2. Description of the Related Art
FIGS. 1A and 1B show a memory cell in a dynamic access memory which comprises a capacitor, transistor and bit line contact. FIG. 1B shows a cross-sectional view as taken along line A--A in FIG. 1A. In the memory cell, transfer transistor (MOS transistor) 10 is made up of gate 2, source 4a and drain 4b. With the gate voltage of transfer transistor 10 raised, a signal to bit line 1 is written as data into a capacitor between capacitor plate 3 and substrate 8 via transfer transistor 10 and, with the aforementioned gate voltage lowered and hence MOS transistor 10 OFF, is stored as data. At the read time, on the other hand, the gate voltage of transfer transistor 10 is raised and hence MOS transistor 10 is turned ON. A corresponding voltage is sent to bit line and then amplified by a sense amplifier which is connected to the bit line. It is thus judged whether data is "0" or "1". The semiconductor device of FIG. 1B includes insulating interlayer 5, capacitor gate insulating film 6, transfer transistor insulating film 9 and bit line contact 11.
FIGS. 2A and 2B show a cell array corresponding to the memory as shown in FIGS. 1A and 1B. Bit line 1 extends over cell element area 20 and is connected to bit line contact 11 for each respective cell element area 20. In the cell array, reference numeral 2 shows gate 1 bit line; 4, source and drain regions; 5, an insulating interlayer; 6, a capacitor gate insulating film; 7, a transfer transistor insulating film; 9, a field insulating film; and 11, a bit line contact.
When a greater number of contact holes for bit line contact formation are to be formed in a semiconductor layer structure, some of them are left unopened. In order to raise the electrical conductivity, which is the ratio between an actual number of contact holes as distinct from a total number of holes formed and those contact holes left unopened, it is necessary to form bigger contact holes. As a result, a flat bit line width (twice an X value in FIG. 1A) is narrowed around the contact hole, causing an increase in bit line resistance and hence a margin drop in the memory cell's sense amplifier operation.
In order to cope with the aforementioned drawback, an attempt has been made to thicken bit line 1 around bit line contact 11, that is, to increase the X value. In the conventional cell pattern, however, if the aforementioned X value is increased, then the distance between bit lines 1 is decreased, causing the occurrence of a short between the bit lines. In the cell pattern, it appears possible to increase the X value if an alternate array of bit line contact 11 on upper bit line 1 and bit line contact 11 on lower bit line 1 is employed. It is, however, difficult to change the cell array shown in FIGS. 2A and 2B, because the cell array of FIG. 2 is of a folded bit line type.
The following explains why the bit lines' resistance rises in the conventional system.
It is necessary to lower the bit lines' resistance because a rise in the bit line's resistance occurs due to the deposition of a silicide film by an ordinary sputtering method. That is, this occurs due to the prominent thinning of the silicide film at the contact site resulting from a poor converage rate at the contact area, that is, the ratio between the vertical thickness of the bit line at the contact site and the thickness of the flat area of the bit line relative to the contact site. In order to solve the problem, it is preferable that the silicide film be deposited on the associated semiconductor structure by virtue of a vacuum CVD method by which a high degree of coverage is obtained at the corner site and groove area. However, the method is now at the development stage and cannot be introduced in the production line of LSI's.